3D integration of integrated circuits is becoming a prominent solution in the design of high performance chips. Multiple dies can be stacked in a single 3D structure and utilizes Through Silicon Vias (TSV) for die to die communications. While this feature significantly decrease the latency of data transfer, multi-tier stacking will increase the power density within the 3D structure. Furthermore, each additional stacked die represents additional thermal resistance in the path of cooling, thus deceasing the cooling efficiency of the 3D stack. Overlapping power density blocks will aggregate temperature hotspots across several layers, creating volumetric hotspots. Therefore the temperature sensing and management of 3D IC is critical to any future 3D design. Thermoelectric devices can sense temperature gradients and harvest this gradient for energy saving purposes. They can also be made as on-chip thin film devices on the same order of thickness as CMOS metal layers. In this report, we propose the integration of thermoelectric devices in 3D IC for temperature sensing, management, and energy harvesting purposes. First we present a novel architecture for embedding bi-metallic thermocouple based temperature sensors into 3D IC stacks. Our architecture uses dedicated TSVs to thermally couple sensors in the metal layer with the hotspots to be monitored in the active layer throughout the multi-stack structures. Through thermal modeling and simulation, we demonstrate that we can achieve high accuracy (less than 1 ºC error) in temperature tracking while still maintaining the effectiveness of the Thermal TSVs in heat management (conforming to a fixed peak temperature threshold such as 95 ºC). Second, we present a full system integration of a thermoelectric energy harvesting system as an on-chip component into a 3D IC. Our system incorporates a lithographically patterned bi-metallic thin-film thermocouple network with a switched capacitor power converter and a charge buffer capacitor to harvest thermal energy produced by temperature gradients in typical 3D IC structures. The proposed integration of thermocouples into 3D IC enable us to monitor temperature within the 3D structure and at the same time harvest the potential thermal energy present in high performance 3D chips. Third, we presented a methodology for constructing a power model for associative memories based on small-scale circuit-level power analysis combined with behavioral modeling of transition activity. We implemented our power model on a real CAM chip, Fermilab’s 3D pattern recognition VIPRAM00. We showed that our model is capable of predicting the total average power to within 4% of the measurement power. Fourth, recognizing the important performance impact of the processor layer thermal footprint in 3D DRAM designs, we propose an adaptive thermal management scheme that utilizes the CPU frequency modulation in order to maintain the 3D DRAM cache in the lower refresh rate states. Lastly, we focus on the thermal management of 3D silicon photonic circuits. We investigated different material, heater configurations, heater power while implementing our thin-film thermocouple array to detect and minimizing on-chip temperature gradient for silicon photonic layers.

Last modified

• 04/16/2018

Creator

• Dawei Li

DOI

• https://doi.org/10.21985/N2TM4P

Subject

• Computer Engineering

Keyword

• SRAM
• Power Modeling
• DRAM
• TSV
• CAM
• 3D IC

Date created

• 2017-01-01

Resource type

• Dissertation

Rights statement

• In Copyright