Timing Analysis and Optimization Techniques for High Performance Integrated Circuits

Ahmed Shebaita

doi:https://doi.org/10.21985/N2SJ05

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Timing Analysis and Optimization Techniques for High Performance Integrated Circuits

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As manufacturing technology moves toward fundamental limits of silicon CMOS processing, it is increasingly important to utilize the full potential of available transistors and interconnects. While manufacturing technology faces fundamental limits inherent in physical laws or material properties, design and verification technology faces fundamental limitations inherent in the computational intractability of design optimizations and in the broad and unknown range of potential applications within various design processes. In this research, we explore how design and verification technology can enable the implementation of single-chip microelectronic systems that take full advantage of manufacturing technology with respect to such criteria as complexity, performance, and power dissipation. One limitation is that the integrated circuit (IC) analysis and verification process involves practical tradeoffs among multiple objectives. For example, there is a need to apply a correct full model that is computationally very efficient in terms of both run time and resource usage. A second limitation is in the integrated circuit design process which again involves practical tradeoffs among multiple objectives such as performance, power dissipation, reliability, etc. In today's highly competitive environment, even small differences in the quality of one process versus another can be the difference between success and failure, and a major improvement in quality can lead to an entirely new generation of commercial tools and services. This research handles the verification, modeling and optimization problems of current technologies. For analysis and verification purposes, new techniques to handle both the inductance effects and the nonlinear gate behavior effects are presented. A new technique of time shifted moment matching (TSMM) performs moment matching (for expansion around s=0) on a time-shifted version of the original signal. Existing model order reduction techniques were highly improved by applying the time shifted moment's concept. Including inductance in static timing analysis for better delay and rise time estimations become possible by both introducing a generalized driving point admittance which takes the inductive shielding into consideration and introducing a more general waveform shape that accounts for the nonmonotonic behavior due to inductance effects. To account for the nonlinear behavior of the gate in static timing analysis, while preserving the minimum complexity and utmost flexibility, a novel representation of the gate is introduced which linearizes the gate around a given load. Hence, moment propagation and uniform treatment of the gates and interconnect becomes possible for the first time. For modeling purposes, this research handles one of the most critical phenomena that appear in the multi GHZ chips, namely skin effect. Figures of merit to determine when skin effect becomes important and require volume discretization modeling in the GHZ range is presented. This derived figure of merit is shown to depend solely on the interconnect dimensions and spacing and is independent of the type of materials used or technology scaling. The model has put a much tighter bound on which interconnect requires to have the volume descritized model than the existing models. Finally, a novel optimization technique that minimizes a cost function of both the propagation delay and power consumption of CMOS tapered buffers is presented. A slight increase in the threshold voltage is shown to have an exponential effect in reducing the total power dissipation. The corresponding increase in the propagation delay is compensated for by increasing the number of buffer stages such that there is still an overall significant improvement in both the propagation delay and the total power dissipation.

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